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Re: [PATCH 03/24] target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH 03/24] target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
Date: Mon, 11 Dec 2023 22:27:08 +0100
User-agent: Mozilla Thunderbird

On 11/12/23 22:19, Philippe Mathieu-Daudé wrote:
accel/tcg/ files requires the following definitions:

   - TARGET_LONG_BITS
   - TARGET_PAGE_BITS
   - TARGET_PHYS_ADDR_SPACE_BITS
   - TCG_GUEST_DEFAULT_MO

The first 3 are defined in "cpu-param.h". The last one
in "cpu.h", with a bunch of definitions irrelevant for
TCG. By moving the TCG_GUEST_DEFAULT_MO definition to
"cpu-param.h", we can simplify various accel/tcg includes.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
  target/alpha/cpu-param.h      |  3 +++
  target/alpha/cpu.h            |  3 ---
  target/arm/cpu-param.h        |  8 +++++---
  target/arm/cpu.h              |  3 ---
  target/avr/cpu-param.h        |  2 ++
  target/avr/cpu.h              |  2 --
  target/hppa/cpu-param.h       |  6 ++++++
  target/hppa/cpu.h             |  6 ------
  target/i386/cpu-param.h       |  3 +++
  target/i386/cpu.h             |  3 ---
  target/loongarch/cpu-param.h  |  2 ++
  target/loongarch/cpu.h        |  2 --
  target/microblaze/cpu-param.h |  3 +++
  target/microblaze/cpu.h       |  3 ---
  target/mips/cpu-param.h       |  2 ++
  target/mips/cpu.h             |  2 --
  target/openrisc/cpu-param.h   |  2 ++
  target/openrisc/cpu.h         |  2 --
  target/ppc/cpu-param.h        |  2 ++
  target/ppc/cpu.h              |  2 --
  target/riscv/cpu-param.h      |  2 ++
  target/riscv/cpu.h            |  2 --
  target/s390x/cpu-param.h      |  6 ++++++
  target/s390x/cpu.h            |  3 ---
  target/sparc/cpu-param.h      | 23 +++++++++++++++++++++++
  target/sparc/cpu.h            | 23 -----------------------
  target/xtensa/cpu-param.h     |  3 +++
  target/xtensa/cpu.h           |  3 ---
  28 files changed, 64 insertions(+), 62 deletions(-)


diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index bb3d7ef6f7..4548103a18 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -21,4 +21,10 @@
#define TARGET_PAGE_BITS 12 +/* PA-RISC 1.x processors have a strong memory model. */
+/* ??? While we do not yet implement PA-RISC 2.0, those processors have
+   a weak memory model, but with TLB bits that force ordering on a per-page
+   basis.  It's probably easier to fall back to a strong memory model.  */

Forgot to squash:

-- >8 --
@@ -24,5 +24,7 @@
 /* PA-RISC 1.x processors have a strong memory model.  */
-/* ??? While we do not yet implement PA-RISC 2.0, those processors have
-   a weak memory model, but with TLB bits that force ordering on a per-page
-   basis.  It's probably easier to fall back to a strong memory model.  */
+/*
+ * ??? While we do not yet implement PA-RISC 2.0, those processors have
+ * a weak memory model, but with TLB bits that force ordering on a per-page
+ * basis.  It's probably easier to fall back to a strong memory model.
+ */
---

+#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
+
  #endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 8be45c69c9..6b10ab20ba 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -25,12 +25,6 @@
  #include "qemu/cpu-float.h"
  #include "qemu/interval-tree.h"
-/* PA-RISC 1.x processors have a strong memory model. */
-/* ??? While we do not yet implement PA-RISC 2.0, those processors have
-   a weak memory model, but with TLB bits that force ordering on a per-page
-   basis.  It's probably easier to fall back to a strong memory model.  */
-#define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
-
  #define MMU_ABS_W_IDX     6
  #define MMU_ABS_IDX       7
  #define MMU_KERNEL_IDX    8




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