Re: [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV

[Alistair Francis]

On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> If CPU does not implement the Vector extension, it usually means
> mstatus vs hardwire to zero. So we should not allow write a
> non-zero value to this field.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/csr.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fde7ce1a53..d1de6b2390 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1328,11 +1328,14 @@ static RISCVException write_mstatus(CPURISCVState 
> *env, int csrno,
>      mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
>          MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
>          MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> -        MSTATUS_TW | MSTATUS_VS;
> +        MSTATUS_TW;
>
>      if (riscv_has_ext(env, RVF)) {
>          mask |= MSTATUS_FS;
>      }
> +    if (riscv_has_ext(env, RVV)) {
> +        mask |= MSTATUS_VS;
> +    }
>
>      if (xl != MXL_RV32 || env->debugger) {
>          if (riscv_has_ext(env, RVH)) {
> --
> 2.25.1
>
>