Re: [PATCH for-9.0 0/5] target/riscv/kvm: fix KVM reg id sizes

[Alistair Francis]

On Sat, Dec 9, 2023 at 4:40 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> While working in a follow-up for the Vector KVM regs, where we would
> read 'vlenb' and then all other vregs [1], Drew noticed that we're using
> kvm_riscv_reg_id() in registers that are u32 and u64.
>
> The helper is returning ulong regs for all cases, meaning that we return
> the wrong size for u32 regs when running 6 in 64 bits (case of FP_F
> regs) and u64 regs when running in 32 bits (case of FP_D and timer
> regs).
>
> It's best to do a quick bug fix round in the KVM reg IDs before adding
> more IDs, so here we are.
>
> This is marked as 9.0 because the fixes aren't critical enough to
> postpone 8.2. Michael, patches 1, 2 and 3 are good candidates for
> 8.2-stable.
>
> Alistair, in case these are accepted I'll re-send "[PATCH for-9.0 0/4]
> target/riscv: add RVV CSRs" based on these fixes to avoid conflicts in
> the tree.
>
>
> [1] this is dependent on kernel side changes that are being discussed
> here: 
> https://lore.kernel.org/kvm/20231205174509.2238870-1-dbarboza@ventanamicro.com/
> ("[PATCH v3 0/3] RISC-V, KVM: add 'vlenb' and vector CSRs to get-reg-list")
>
>
> Daniel Henrique Barboza (5):
>   target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
>   target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64
>   target/riscv/kvm: change timer regs size to u64
>   target/riscv/kvm: add RISCV_CONFIG_REG()
>   target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/kvm/kvm-cpu.c | 109 ++++++++++++++++++++-----------------
>  1 file changed, 59 insertions(+), 50 deletions(-)
>
> --
> 2.41.0
>
>