Re: [PATCH 1/2] target/riscv/csr: Rename groups of interrupts

[Daniel Henrique Barboza]

On 12/21/23 08:36, Vadim Shakirov wrote:
> In AIA spec in 5.1 chapter says that "... the AIA categorizes the counter
> overflow interrupt (code 13) as a local interrupt. It is assumed furthermore
> that any future definitions for reserved interrupt numbers 14 and 15 will
> also be local interrupts" and than LCOFI belongs to LOCAL_INTERRUPTS
>
> Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/csr.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d69bff5a67..36f807d5f6 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1120,18 +1120,18 @@ static RISCVException write_stimecmph(CPURISCVState 
> *env, int csrno,
>   /* Machine constants */
>   
>   #define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
> -#define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \
> -                                      MIP_LCOFIP))
> +#define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
>   #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
>   #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
> +#define LOCAL_INTERRUPTS   ((uint64_t)(MIP_LCOFIP))
>   
>   #define VSTOPI_NUM_SRCS 5
>   
>   static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
> -                                           VS_MODE_INTERRUPTS;
> +                                      VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS;
>   static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
>   static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
> -                                     HS_MODE_INTERRUPTS;
> +                                HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS;
>   #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
>                            (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
>                            (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
> @@ -1163,7 +1163,7 @@ static const target_ulong sstatus_v1_10_mask = 
> SSTATUS_SIE | SSTATUS_SPIE |
>       SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
>       SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
>   static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
> -                                              SIP_LCOFIP;
> +                                              LOCAL_INTERRUPTS;
>   static const target_ulong hip_writable_mask = MIP_VSSIP;
>   static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
>                                                  MIP_VSEIP;
> @@ -2471,7 +2471,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, int 
> csrno,
>                                   uint64_t new_val, uint64_t wr_mask)
>   {
>       RISCVException ret;
> -    uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
> +    uint64_t mask = env->mideleg & (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS);
>   
>       if (env->virt_enabled) {
>           if (env->hvictl & HVICTL_VTI) {
> @@ -2693,7 +2693,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, int 
> csrno,
>       }
>   
>       if (ret_val) {
> -        *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
> +        *ret_val &= env->mideleg & (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS);
>       }
>   
>       return ret;