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[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type
From: |
Rob Bradford |
Subject: |
[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type |
Date: |
Tue, 9 Jan 2024 17:07:37 +0000 |
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
target/riscv/tcg/tcg-cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f10871d352..9705daec93 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -999,7 +999,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
- riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+ riscv_cpu_set_misa(env, env->misa_mxl,
+ env->misa_ext | RVG | RVJ | RVV | RVB);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
--
2.43.0
- Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, (continued)
- Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
- Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
- Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Rob Bradford, 2024/01/11
- Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/12
- Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Rob Bradford, 2024/01/12
- Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Ved Shanbhogue, 2024/01/12
Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
[PATCH 2/3] target/riscv: Add step to validate 'B' extension, Rob Bradford, 2024/01/09
[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type,
Rob Bradford <=