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Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type


From: Daniel Henrique Barboza
Subject: Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type
Date: Wed, 10 Jan 2024 15:41:10 -0300
User-agent: Mozilla Thunderbird

Rob,

Given that you'll need to resend the patches due to the conflict in patch 2,
I think it would be nice to mention in this commit message that we're ok with
enabling RVB in the 'max' CPU, even though RVB per se is experimental, because
it's just an alias for extensions that the CPU already uses.

I'm asking this because future Daniel will forget why we're adding an 
experimental
extension in the 'max' CPU, and this info in the commit msg will spare him from
searching the ML archives to discover why :)



Thanks,

Daniel

On 1/10/24 15:32, Daniel Henrique Barboza wrote:


On 1/9/24 14:07, Rob Bradford wrote:
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
  target/riscv/tcg/tcg-cpu.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f10871d352..9705daec93 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -999,7 +999,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
      const RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa(env, env->misa_mxl,
+                       env->misa_ext | RVG | RVJ | RVV | RVB);

I'm aware that we decided a while ago the 'max' CPU could only have non-vendor 
and
non-experimental extensions enabled. RVB is experimental, so in theory we 
shouldn't
enable it.

But RVB is an alias for zba, zbb and zbs, extensions that the 'max' CPU is 
already
enabling. In this case I think it's sensible to enable RVB here since it would 
just
reflect stuff that it's already happening.


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>




      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
          isa_ext_update_enabled(cpu, prop->offset, true);



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