Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

[Rob Bradford]

+ Ved

On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote:
> On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> > On Tue, Jan 09, 2024 at 05:07:35PM +0000, Rob Bradford wrote:
> > > Add the infrastructure for the 'B' extension which is the union
> > > of the
> > > Zba, Zbb and Zbs instructions.
> > > 
> > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> > > ---
> > >  target/riscv/cpu.c         | 5 +++--
> > >  target/riscv/cpu.h         | 1 +
> > >  target/riscv/tcg/tcg-cpu.c | 1 +
> > >  3 files changed, 5 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index b07a76ef6b..22f8e527ff 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -38,9 +38,9 @@
> > >  #include "tcg/tcg.h"
> > >  
> > >  /* RISC-V CPU definitions */
> > > -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
> > > +static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
> > 
> > Is there a corresponding proposed change to table 29.1 of the
> > nonpriv spec
> > which states B comes after C and before P? If so, can you provide a
> > link
> > to it? Otherwise, how do we know that?
> 
> Oh, I see. The unpriv spec B chapter comes after the C chapter (and
> before
> J, P, ...). I still wonder if we'll have a 29.1 table update with the
> ratification of this extension though.
> 
> 

I agree it's a bit confusing - but the order is established by the
table in the unprivileged spec and the table explanation also makes
this clear.

"""
Table 27.1: Standard ISA extension names. The table also defines the
canonical order in which
extension names must appear in the name string, with top-to-bottom in
table indicating first-to-last
in the name string, e.g., RV32IMACV is legal, whereas RV32IMAVC is not.
"""

The proposed B specification does not make any remarks about the
ordering in the ISA definition string. [1] I would worry there would be
a lot of software churn if this ordering were to be changed.

Cheers,

Rob

> Thanks,
> drew

[1] - https://github.com/riscv/riscv-b