qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v4 17/17] target/riscv/cpu.c: move 'marchid' to riscv_cpu_pro


From: Alistair Francis
Subject: Re: [PATCH v4 17/17] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]
Date: Fri, 12 Jan 2024 11:37:23 +1000

On Sat, Jan 6, 2024 at 9:09 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Keep all class properties in riscv_cpu_properties[].
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 110 +++++++++++++++++++++++----------------------
>  1 file changed, 57 insertions(+), 53 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6149f5960e..3870c3a433 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2044,6 +2044,62 @@ static const PropertyInfo prop_mimpid = {
>      .set = prop_mimpid_set,
>  };
>
> +static void prop_marchid_set(Object *obj, Visitor *v, const char *name,
> +                             void *opaque, Error **errp)
> +{
> +    bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
> +    RISCVCPU *cpu = RISCV_CPU(obj);
> +    uint64_t prev_val = cpu->cfg.marchid;
> +    uint64_t value, invalid_val;
> +    uint32_t mxlen = 0;
> +
> +    if (!visit_type_uint64(v, name, &value, errp)) {
> +        return;
> +    }
> +
> +    if (!dynamic_cpu && prev_val != value) {
> +        error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
> +                   object_get_typename(obj), prev_val);
> +        return;
> +    }
> +
> +    switch (riscv_cpu_mxl(&cpu->env)) {
> +    case MXL_RV32:
> +        mxlen = 32;
> +        break;
> +    case MXL_RV64:
> +    case MXL_RV128:
> +        mxlen = 64;
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +
> +    invalid_val = 1LL << (mxlen - 1);
> +
> +    if (value == invalid_val) {
> +        error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
> +                         "and the remaining bits zero", mxlen);
> +        return;
> +    }
> +
> +    cpu->cfg.marchid = value;
> +}
> +
> +static void prop_marchid_get(Object *obj, Visitor *v, const char *name,
> +                             void *opaque, Error **errp)
> +{
> +    uint64_t value = RISCV_CPU(obj)->cfg.marchid;
> +
> +    visit_type_uint64(v, name, &value, errp);
> +}
> +
> +static const PropertyInfo prop_marchid = {
> +    .name = "marchid",
> +    .get = prop_marchid_get,
> +    .set = prop_marchid_set,
> +};
> +
>  /*
>   * RVA22U64 defines some 'named features' or 'synthetic extensions'
>   * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
> @@ -2132,6 +2188,7 @@ static Property riscv_cpu_properties[] = {
>
>       {.name = "mvendorid", .info = &prop_mvendorid},
>       {.name = "mimpid", .info = &prop_mimpid},
> +     {.name = "marchid", .info = &prop_marchid},
>
>  #ifndef CONFIG_USER_ONLY
>      DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
> @@ -2213,56 +2270,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
>  };
>  #endif
>
> -static void cpu_set_marchid(Object *obj, Visitor *v, const char *name,
> -                            void *opaque, Error **errp)
> -{
> -    bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
> -    RISCVCPU *cpu = RISCV_CPU(obj);
> -    uint64_t prev_val = cpu->cfg.marchid;
> -    uint64_t value, invalid_val;
> -    uint32_t mxlen = 0;
> -
> -    if (!visit_type_uint64(v, name, &value, errp)) {
> -        return;
> -    }
> -
> -    if (!dynamic_cpu && prev_val != value) {
> -        error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
> -                   object_get_typename(obj), prev_val);
> -        return;
> -    }
> -
> -    switch (riscv_cpu_mxl(&cpu->env)) {
> -    case MXL_RV32:
> -        mxlen = 32;
> -        break;
> -    case MXL_RV64:
> -    case MXL_RV128:
> -        mxlen = 64;
> -        break;
> -    default:
> -        g_assert_not_reached();
> -    }
> -
> -    invalid_val = 1LL << (mxlen - 1);
> -
> -    if (value == invalid_val) {
> -        error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
> -                         "and the remaining bits zero", mxlen);
> -        return;
> -    }
> -
> -    cpu->cfg.marchid = value;
> -}
> -
> -static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
> -                           void *opaque, Error **errp)
> -{
> -    uint64_t value = RISCV_CPU(obj)->cfg.marchid;
> -
> -    visit_type_uint64(v, name, &value, errp);
> -}
> -
>  static void riscv_cpu_class_init(ObjectClass *c, void *data)
>  {
>      RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -2293,9 +2300,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void 
> *data)
>      cc->gdb_arch_name = riscv_gdb_arch_name;
>      cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
>
> -    object_class_property_add(c, "marchid", "uint64", cpu_get_marchid,
> -                              cpu_set_marchid, NULL, NULL);
> -
>      device_class_set_props(dc, riscv_cpu_properties);
>  }
>
> --
> 2.43.0
>
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]