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Re: [PATCH v3 05/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb
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From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v3 05/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' |
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Date: |
Mon, 22 Jan 2024 12:58:16 +1000 |
On Wed, Jan 17, 2024 at 7:00 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
> "s->cfg_ptr->vlen >> 3".
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 140 ++++++++++++------------
> 1 file changed, 70 insertions(+), 70 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 3871f0ea73..d743675262 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -217,7 +217,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli
> *a)
> /* vector register offset from env */
> static uint32_t vreg_ofs(DisasContext *s, int reg)
> {
> - return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8;
> + return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlenb;
> }
>
> /* check functions */
> @@ -627,11 +627,11 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
> uint32_t data,
> * As simd_desc supports at most 2048 bytes, and in this implementation,
> * the max vector group length is 4096 bytes. So split it into two parts.
> *
> - * The first part is vlen in bytes, encoded in maxsz of simd_desc.
> + * The first part is vlen in bytes (vlenb), encoded in maxsz of
> simd_desc.
> * The second part is lmul, encoded in data of simd_desc.
> */
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> @@ -791,8 +791,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1,
> uint32_t rs2,
> mask = tcg_temp_new_ptr();
> base = get_gpr(s, rs1, EXT_NONE);
> stride = get_gpr(s, rs2, EXT_NONE);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> @@ -897,8 +897,8 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,
> uint32_t vs2,
> mask = tcg_temp_new_ptr();
> index = tcg_temp_new_ptr();
> base = get_gpr(s, rs1, EXT_NONE);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
> @@ -1036,8 +1036,8 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1,
> uint32_t data,
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> base = get_gpr(s, rs1, EXT_NONE);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> @@ -1086,7 +1086,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1,
> uint32_t nf,
> uint32_t width, gen_helper_ldst_whole *fn,
> DisasContext *s, bool is_store)
> {
> - uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
> + uint32_t evl = s->cfg_ptr->vlenb * nf / width;
> TCGLabel *over = gen_new_label();
> tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
>
> @@ -1096,8 +1096,8 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1,
> uint32_t nf,
>
> uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
> dest = tcg_temp_new_ptr();
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> base = get_gpr(s, rs1, EXT_NONE);
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> @@ -1199,8 +1199,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn
> *gvec_fn,
> data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
> - tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data, fn);
> + tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data, fn);
> }
> mark_vs_dirty(s);
> gen_set_label(over);
> @@ -1248,8 +1248,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1,
> uint32_t vs2, uint32_t vm,
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> data = FIELD_DP32(data, VDATA, VMA, s->vma);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
> @@ -1410,8 +1410,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm,
> uint32_t vs2, uint32_t vm,
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> data = FIELD_DP32(data, VDATA, VMA, s->vma);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
> @@ -1492,8 +1492,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1),
> vreg_ofs(s, a->rs2),
> - tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8,
> + tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb,
> data, fn);
> mark_vs_dirty(s);
> gen_set_label(over);
> @@ -1568,8 +1568,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1),
> vreg_ofs(s, a->rs2),
> - tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data, fn);
> + tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data, fn);
> mark_vs_dirty(s);
> gen_set_label(over);
> return true;
> @@ -1639,8 +1639,8 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1,
> uint32_t vs2, uint32_t vm,
> data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
> - vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data, fn);
> + vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data, fn);
> mark_vs_dirty(s);
> gen_set_label(over);
> return true;
> @@ -1831,8 +1831,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2036,8 +2036,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v
> *a)
> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
>
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> - tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data,
> + tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data,
> fns[s->sew]);
> gen_set_label(over);
> }
> @@ -2082,8 +2082,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x
> *a)
> };
>
> tcg_gen_ext_tl_i64(s1_i64, s1);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
> fns[s->sew](dest, s1_i64, tcg_env, desc);
> }
> @@ -2121,8 +2121,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i
> *a)
>
> s1 = tcg_constant_i64(simm);
> dest = tcg_temp_new_ptr();
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
> fns[s->sew](dest, s1, tcg_env, desc);
>
> @@ -2275,8 +2275,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2303,8 +2303,8 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1,
> uint32_t vs2,
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
> @@ -2391,8 +2391,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2465,8 +2465,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2581,8 +2581,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
> data = FIELD_DP32(data, VDATA, VMA, s->vma);
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), tcg_env,
> - s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data, fn);
> + s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data, fn);
> mark_vs_dirty(s);
> gen_set_label(over);
> return true;
> @@ -2691,8 +2691,8 @@ static bool trans_vfmv_v_f(DisasContext *s,
> arg_vfmv_v_f *a)
> do_nanbox(s, t1, cpu_fpr[a->rs1]);
>
> dest = tcg_temp_new_ptr();
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
> tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
>
> fns[s->sew - 1](dest, t1, tcg_env, desc);
> @@ -2770,8 +2770,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
> \
> data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2821,8 +2821,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
> \
> data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2888,8 +2888,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
> \
> data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew - 1]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -2937,8 +2937,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
> \
> data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, \
> fns[s->sew]); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -3027,8 +3027,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a)
> \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), tcg_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, fn); \
> + s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, data, fn); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> return true; \
> @@ -3061,8 +3061,8 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> dst = dest_gpr(s, a->rd);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
> tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> @@ -3090,8 +3090,8 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> dst = dest_gpr(s, a->rd);
> - desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data));
> + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data));
>
> tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
> tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
> @@ -3128,8 +3128,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
> \
> data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
> vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
> - tcg_env, s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, \
> + tcg_env, s->cfg_ptr->vlenb, \
> + s->cfg_ptr->vlenb, \
> data, fn); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> @@ -3171,8 +3171,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m
> *a)
> };
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), tcg_env,
> - s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data, fns[s->sew]);
> + s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data, fns[s->sew]);
> mark_vs_dirty(s);
> gen_set_label(over);
> return true;
> @@ -3200,8 +3200,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> gen_helper_vid_v_w, gen_helper_vid_v_d,
> };
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> - tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8,
> + tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb,
> data, fns[s->sew]);
> mark_vs_dirty(s);
> gen_set_label(over);
> @@ -3620,8 +3620,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r
> *a)
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
> - tcg_env, s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data,
> + tcg_env, s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data,
> fns[s->sew]);
> mark_vs_dirty(s);
> gen_set_label(over);
> @@ -3641,7 +3641,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME *
> a) \
> vext_check_isa_ill(s) && \
> QEMU_IS_ALIGNED(a->rd, LEN) && \
> QEMU_IS_ALIGNED(a->rs2, LEN)) { \
> - uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
> + uint32_t maxsz = s->cfg_ptr->vlenb * LEN; \
> if (s->vstart_eq_zero) { \
> tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
> vreg_ofs(s, a->rs2), maxsz, maxsz); \
> @@ -3723,8 +3723,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a,
> uint8_t seq)
>
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> vreg_ofs(s, a->rs2), tcg_env,
> - s->cfg_ptr->vlen / 8,
> - s->cfg_ptr->vlen / 8, data, fn);
> + s->cfg_ptr->vlenb,
> + s->cfg_ptr->vlenb, data, fn);
>
> mark_vs_dirty(s);
> gen_set_label(over);
> --
> 2.43.0
>
>
- [PATCH v3 00/13] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen', Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 01/13] target/riscv: add 'vlenb' field in cpu->cfg, Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 02/13] target/riscv/csr.c: use 'vlenb' instead of 'vlen', Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 03/13] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen', Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 04/13] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb, Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 05/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb', Daniel Henrique Barboza, 2024/01/16
- Re: [PATCH v3 05/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb',
Alistair Francis <=
- [PATCH v3 06/13] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb', Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 07/13] target/riscv/vector_helper.c: use 'vlenb', Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 08/13] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl), Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 09/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ(), Daniel Henrique Barboza, 2024/01/16
- [PATCH v3 10/13] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax(), Daniel Henrique Barboza, 2024/01/16