Re: [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking

[Alistair Francis]

On Tue, Jan 9, 2024 at 9:33 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c     | 22 ++++++++++++++++------
>  target/riscv/vector_helper.c | 13 +++++++++++++
>  2 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2c89d749c0..457de381c7 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -579,8 +579,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int 
> imm)
>      TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
>      tcg_gen_addi_tl(addr, src1, imm);
> -    if (get_address_xl(ctx) == MXL_RV32) {
> -        tcg_gen_ext32u_tl(addr, addr);
> +    if (ctx->addr_signed) {
> +        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
> +    } else {
> +        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
>      }
>
>      return addr;
> @@ -593,8 +595,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int 
> rs1, TCGv offs)
>      TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
>      tcg_gen_add_tl(addr, src1, offs);
> -    if (get_xl(ctx) == MXL_RV32) {
> -        tcg_gen_ext32u_tl(addr, addr);
> +    if (ctx->addr_signed) {
> +        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
> +    } else {
> +        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
>      }
>      return addr;
>  }
> @@ -1179,8 +1183,14 @@ static void 
> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
>      ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
>      ctx->cs = cs;
> -    ctx->addr_width = 0;
> -    ctx->addr_signed = false;
> +    if (get_xl(ctx) == MXL_RV32) {
> +        ctx->addr_width = 32;
> +        ctx->addr_signed = false;
> +    } else {
> +        int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
> +        ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm);
> +        ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
> +    }
>      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
>      ctx->zero = tcg_constant_tl(0);
>      ctx->virt_inst_excp = false;
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 8e7a8e80a0..ff1178723c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -94,6 +94,19 @@ static inline uint32_t vext_max_elems(uint32_t desc, 
> uint32_t log2_esz)
>
>  static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
>  {
> +    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> +    if (pmm == PMM_FIELD_DISABLED) {
> +        return addr;
> +    }
> +    int pmlen = riscv_pm_get_pmlen(pmm);
> +    bool signext = riscv_cpu_virt_mem_enabled(env);
> +    addr = addr << pmlen;
> +    /* sign/zero extend masked address by N-1 bit */
> +    if (signext) {
> +        addr = (target_long)addr >> pmlen;
> +    } else {
> +        addr = addr >> pmlen;
> +    }
>      return addr;
>  }
>
> --
> 2.34.1
>
>