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[PATCH v4 0/2] riscv: support new isa extension detection devicetree pro


From: Conor Dooley
Subject: [PATCH v4 0/2] riscv: support new isa extension detection devicetree properties
Date: Wed, 24 Jan 2024 12:55:48 +0000

From: Conor Dooley <conor.dooley@microchip.com>

Making it a series to keep the standalone change to riscv_isa_string()
that Drew reported separate.

Changes in v4:
- Other than a rebase, add a helper for the mxl_max to xlen conversion

Changes in v3:
- g_free() isa_extensions too
- use misa_mxl_max rather than the compile target for the base isa
- add a new patch changing riscv_isa_string() to do the same
- drop a null check that cannot be null
- rebased on top of Alistair's next branch

Changes in v2:
- use g_strdup() for multiletter extension string copying
- wrap stuff in #ifndef to prevent breaking the user mode build
- rename riscv_isa_set_props() -> riscv_isa_write_fdt()

CC: Alistair Francis <Alistair.Francis@wdc.com>
CC: Bin Meng <bin.meng@windriver.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Weiwei Li <liwei1518@gmail.com>
CC: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
CC: qemu-riscv@nongnu.org
CC: qemu-devel@nongnu.org

Conor Dooley (2):
  target/riscv: use misa_mxl_max to populate isa string rather than
    TARGET_LONG_BITS
  target/riscv: support new isa extension detection devicetree
    properties

 hw/riscv/sifive_u.c    |  7 ++---
 hw/riscv/spike.c       |  6 ++--
 hw/riscv/virt.c        |  6 ++--
 target/riscv/cpu.c     | 62 +++++++++++++++++++++++++++++++++++++++++-
 target/riscv/cpu.h     |  2 ++
 target/riscv/gdbstub.c |  2 +-
 6 files changed, 70 insertions(+), 15 deletions(-)

-- 
2.43.0




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