[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 0/2] target/riscv: Support mxstatus CSR for thead-c906
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 0/2] target/riscv: Support mxstatus CSR for thead-c906 |
Date: |
Sun, 4 Feb 2024 13:42:26 +0800 |
This patch set fix the regression on kernel pointed by Björn Töpel in
https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html.
We first add a framework for vendor CSRs in patch 1. After that we add
one thead-c906 CSR mxstatus, which is used for mmu extension xtheadmaee.
thead-c906 uses some flags in pte [60-63] bits. It has history reasons that
SVPBMT didn't exist when thead-c906 came to wotrld. We named this feature as
xtheadmaee[1]. this feature is controlled by an custom CSR named mxstatus,
whose maee field encodes whether enable the pte [60-63] bits.
[1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc
LIU Zhiwei (2):
target/riscv: Register vendors CSR
target/riscv: Support xtheadmaee for thead-c906
target/riscv/cpu.c | 9 ++++++
target/riscv/cpu.h | 9 ++++++
target/riscv/cpu_bits.h | 6 ++++
target/riscv/cpu_cfg.h | 4 ++-
target/riscv/cpu_helper.c | 25 ++++++++-------
target/riscv/meson.build | 1 +
target/riscv/tcg/tcg-cpu.c | 25 ++++++++++++++-
target/riscv/tcg/tcg-cpu.h | 1 +
target/riscv/xthead_csr.c | 65 ++++++++++++++++++++++++++++++++++++++
9 files changed, 132 insertions(+), 13 deletions(-)
create mode 100644 target/riscv/xthead_csr.c
--
2.25.1
- [PATCH v2 0/2] target/riscv: Support mxstatus CSR for thead-c906,
LIU Zhiwei <=