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Re: [PATCH] target/riscv: Use RISCVException as return type for all csr
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH] target/riscv: Use RISCVException as return type for all csr ops |
|
Date: |
Mon, 5 Feb 2024 10:22:57 +1000 |
On Tue, Jan 30, 2024 at 10:49 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> The real return value type has been converted to RISCVException,
> but some function declarations still not. This patch makes all
> csr operation declarations use RISCVExcetion.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 117 ++++++++++++++++++++++++++++-----------------
> 1 file changed, 74 insertions(+), 43 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 674ea075a4..ac9a856cc5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -242,7 +242,7 @@ static RISCVException any32(CPURISCVState *env, int csrno)
>
> }
>
> -static int aia_any(CPURISCVState *env, int csrno)
> +static RISCVException aia_any(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_smaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -251,7 +251,7 @@ static int aia_any(CPURISCVState *env, int csrno)
> return any(env, csrno);
> }
>
> -static int aia_any32(CPURISCVState *env, int csrno)
> +static RISCVException aia_any32(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_smaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -269,7 +269,7 @@ static RISCVException smode(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static int smode32(CPURISCVState *env, int csrno)
> +static RISCVException smode32(CPURISCVState *env, int csrno)
> {
> if (riscv_cpu_mxl(env) != MXL_RV32) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -278,7 +278,7 @@ static int smode32(CPURISCVState *env, int csrno)
> return smode(env, csrno);
> }
>
> -static int aia_smode(CPURISCVState *env, int csrno)
> +static RISCVException aia_smode(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -287,7 +287,7 @@ static int aia_smode(CPURISCVState *env, int csrno)
> return smode(env, csrno);
> }
>
> -static int aia_smode32(CPURISCVState *env, int csrno)
> +static RISCVException aia_smode32(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -496,7 +496,7 @@ static RISCVException pointer_masking(CPURISCVState *env,
> int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> -static int aia_hmode(CPURISCVState *env, int csrno)
> +static RISCVException aia_hmode(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -505,7 +505,7 @@ static int aia_hmode(CPURISCVState *env, int csrno)
> return hmode(env, csrno);
> }
>
> -static int aia_hmode32(CPURISCVState *env, int csrno)
> +static RISCVException aia_hmode32(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_ssaia) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -681,7 +681,8 @@ static RISCVException read_vl(CPURISCVState *env, int
> csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_vlenb(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = riscv_cpu_cfg(env)->vlen >> 3;
> return RISCV_EXCP_NONE;
> @@ -742,13 +743,15 @@ static RISCVException write_vstart(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_vcsr(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
> return RISCV_EXCP_NONE;
> }
>
> -static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_vcsr(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> #if !defined(CONFIG_USER_ONLY)
> env->mstatus |= MSTATUS_VS;
> @@ -798,13 +801,15 @@ static RISCVException read_timeh(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hpmcounter(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = get_ticks(false);
> return RISCV_EXCP_NONE;
> }
>
> -static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = get_ticks(true);
> return RISCV_EXCP_NONE;
> @@ -812,7 +817,8 @@ static int read_hpmcounterh(CPURISCVState *env, int
> csrno, target_ulong *val)
>
> #else /* CONFIG_USER_ONLY */
>
> -static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_mhpmevent(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> int evt_index = csrno - CSR_MCOUNTINHIBIT;
>
> @@ -821,7 +827,8 @@ static int read_mhpmevent(CPURISCVState *env, int csrno,
> target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> -static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> int evt_index = csrno - CSR_MCOUNTINHIBIT;
> uint64_t mhpmevt_val = val;
> @@ -837,7 +844,8 @@ static int write_mhpmevent(CPURISCVState *env, int csrno,
> target_ulong val)
> return RISCV_EXCP_NONE;
> }
>
> -static int read_mhpmeventh(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> int evt_index = csrno - CSR_MHPMEVENT3H + 3;
>
> @@ -846,7 +854,8 @@ static int read_mhpmeventh(CPURISCVState *env, int csrno,
> target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> -static int write_mhpmeventh(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> int evt_index = csrno - CSR_MHPMEVENT3H + 3;
> uint64_t mhpmevth_val = val;
> @@ -860,7 +869,8 @@ static int write_mhpmeventh(CPURISCVState *env, int
> csrno, target_ulong val)
> return RISCV_EXCP_NONE;
> }
>
> -static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> int ctr_idx = csrno - CSR_MCYCLE;
> PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> @@ -885,7 +895,8 @@ static int write_mhpmcounter(CPURISCVState *env, int
> csrno, target_ulong val)
> return RISCV_EXCP_NONE;
> }
>
> -static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong
> val)
> +static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> int ctr_idx = csrno - CSR_MCYCLEH;
> PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
> @@ -945,7 +956,8 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState
> *env, target_ulong *val,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hpmcounter(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> uint16_t ctr_index;
>
> @@ -960,7 +972,8 @@ static int read_hpmcounter(CPURISCVState *env, int csrno,
> target_ulong *val)
> return riscv_pmu_read_ctr(env, val, false, ctr_index);
> }
>
> -static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> uint16_t ctr_index;
>
> @@ -975,7 +988,8 @@ static int read_hpmcounterh(CPURISCVState *env, int
> csrno, target_ulong *val)
> return riscv_pmu_read_ctr(env, val, true, ctr_index);
> }
>
> -static int read_scountovf(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_scountovf(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
> int i;
> @@ -1638,7 +1652,8 @@ static RISCVException rmw_mvienh(CPURISCVState *env,
> int csrno,
> return ret;
> }
>
> -static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_mtopi(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> int irq;
> uint8_t iprio;
> @@ -1678,8 +1693,9 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int
> csrno)
> };
> }
>
> -static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
> - target_ulong new_val, target_ulong wr_mask)
> +static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
> + target_ulong *val, target_ulong new_val,
> + target_ulong wr_mask)
> {
> target_ulong *iselect;
>
> @@ -1758,8 +1774,9 @@ static int rmw_iprio(target_ulong xlen,
> return 0;
> }
>
> -static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
> - target_ulong new_val, target_ulong wr_mask)
> +static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
> + target_ulong *val, target_ulong new_val,
> + target_ulong wr_mask)
> {
> bool virt, isel_reserved;
> uint8_t *iprio;
> @@ -1833,8 +1850,9 @@ done:
> return RISCV_EXCP_NONE;
> }
>
> -static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
> - target_ulong new_val, target_ulong wr_mask)
> +static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,
> + target_ulong *val, target_ulong new_val,
> + target_ulong wr_mask)
> {
> bool virt;
> int ret = -EINVAL;
> @@ -3031,7 +3049,8 @@ static RISCVException write_satp(CPURISCVState *env,
> int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_vstopi(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> int irq, ret;
> target_ulong topei;
> @@ -3120,7 +3139,8 @@ static int read_vstopi(CPURISCVState *env, int csrno,
> target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> -static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_stopi(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> int irq;
> uint8_t iprio;
> @@ -3576,19 +3596,21 @@ static RISCVException write_htimedeltah(CPURISCVState
> *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hvictl(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = env->hvictl;
> return RISCV_EXCP_NONE;
> }
>
> -static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_hvictl(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> env->hvictl = val & HVICTL_VALID_MASK;
> return RISCV_EXCP_NONE;
> }
>
> -static int read_hvipriox(CPURISCVState *env, int first_index,
> +static RISCVException read_hvipriox(CPURISCVState *env, int first_index,
> uint8_t *iprio, target_ulong *val)
> {
> int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
> @@ -3614,7 +3636,7 @@ static int read_hvipriox(CPURISCVState *env, int
> first_index,
> return RISCV_EXCP_NONE;
> }
>
> -static int write_hvipriox(CPURISCVState *env, int first_index,
> +static RISCVException write_hvipriox(CPURISCVState *env, int first_index,
> uint8_t *iprio, target_ulong val)
> {
> int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
> @@ -3640,42 +3662,50 @@ static int write_hvipriox(CPURISCVState *env, int
> first_index,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hviprio1(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> return read_hvipriox(env, 0, env->hviprio, val);
> }
>
> -static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_hviprio1(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> return write_hvipriox(env, 0, env->hviprio, val);
> }
>
> -static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hviprio1h(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> return read_hvipriox(env, 4, env->hviprio, val);
> }
>
> -static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_hviprio1h(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> return write_hvipriox(env, 4, env->hviprio, val);
> }
>
> -static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hviprio2(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> return read_hvipriox(env, 8, env->hviprio, val);
> }
>
> -static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_hviprio2(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> return write_hvipriox(env, 8, env->hviprio, val);
> }
>
> -static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_hviprio2h(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> return read_hvipriox(env, 12, env->hviprio, val);
> }
>
> -static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
> +static RISCVException write_hviprio2h(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> return write_hvipriox(env, 12, env->hviprio, val);
> }
> @@ -3699,7 +3729,8 @@ static RISCVException write_vsstatus(CPURISCVState
> *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
> +static RISCVException read_vstvec(CPURISCVState *env, int csrno,
> + target_ulong *val)
> {
> *val = env->vstvec;
> return RISCV_EXCP_NONE;
> --
> 2.25.1
>
>
- Re: [PATCH] target/riscv: Use RISCVException as return type for all csr ops,
Alistair Francis <=