[PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode

[Alvin Chang]

>From the RISC-V debug specification, it defines the following operations
for CSR tcontrol when any trap into M-mode is taken:
1. tcontrol.MPTE is set to the value of tcontrol.MTE
2. tcontrol.MTE is set to 0

This commit implements the above operations into
riscv_cpu_do_interrupt().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
 target/riscv/cpu_helper.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d462d95ee1..037ae21062 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1806,6 +1806,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
             riscv_cpu_set_virt_enabled(env, 0);
         }
 
+        /* Trapping to M-mode. Set tcontrol CSR in debug Sdtrig extension. */
+        s = env->tcontrol;
+        s = set_field(s, TCONTROL_MPTE, get_field(s, TCONTROL_MTE));
+        s = set_field(s, TCONTROL_MTE, 0);
+        env->tcontrol = s;
+
         s = env->mstatus;
         s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
         s = set_field(s, MSTATUS_MPP, env->priv);
-- 
2.34.1