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From: | Daniel Henrique Barboza |
Subject: | Re: [PATCH 4/4] target/riscv: Set the value of CSR tcontrol when mret is executed |
Date: | Fri, 16 Feb 2024 10:23:12 -0300 |
User-agent: | Mozilla Thunderbird |
On 2/16/24 03:13, Alvin Chang wrote:
The RISC-V debug specification defines the following operation for CSR tcontrol when "mret" is executed: - tcontrol.MTE is set to the value of tcontrol.MPTE This commit implements the above operation into helper_mret(). Note that from tech-debug mailing list: https://lists.riscv.org/g/tech-debug/topic/102702615#1461 The debug specification does not mention the operation to tcontrol.MPTE when "mret" is executed. Therefore, we just keep its current value. Signed-off-by: Alvin Chang <alvinga@andestech.com> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
target/riscv/op_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f414aaebdb..12822b3afa 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -347,6 +347,12 @@ target_ulong helper_mret(CPURISCVState *env) mstatus = set_field(mstatus, MSTATUS_MPRV, 0); } env->mstatus = mstatus; + + uint64_t tcontrol = env->tcontrol; + tcontrol = set_field(tcontrol, TCONTROL_MTE, + get_field(tcontrol, TCONTROL_MPTE)); + env->tcontrol = tcontrol; + riscv_cpu_set_mode(env, prev_priv);if (riscv_has_ext(env, RVH)) {
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