Re: [PATCH] target/riscv: Fix shift count overflow

[Daniel Henrique Barboza]

On 2/24/24 10:02, demin.han wrote:
> The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
> and results in wrong vill.
>
> Signed-off-by: demin.han <demin.han@starfivetech.com>
> ---
>   target/riscv/vector_helper.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 84cec73eb2..ced0aca633 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -53,10 +53,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong 
> s1,
>            * VLEN * LMUL >= SEW
>            * VLEN >> (8 - lmul) >= sew
>            * (vlenb << 3) >> (8 - lmul) >= sew
> -         * vlenb >> (8 - 3 - lmul) >= sew
>            */
>           if (vlmul == 4 ||
> -            cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) {
> +            (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) {
>               vill = true;
>           }

Please add a new var:

uint16_t vlen = cpu->cfg.vlenb << 3;

And use it in the 'if' to be more readable:

           if (vlmul == 4 ||
               vlen >> (8 - 3 - vlmul) < sew) {
               vill = true;
           }


Thanks,

Daniel


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