Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

[Daniel Henrique Barboza]

Hi Jason,


We're in the middle of code freeze for the incoming 9.0 release. In this
period the maintainer will only queue bug fixes.

Your support is a new feature, so it'll only be pushed after the release is
done. Current ETA for the release is Apr 16th if there's no rc4. A safe
bet is to expect Alistair to queue the patches in the start of May.


Thanks,

Daniel



Perhaps we should start advertising the freeze dates more clearly in the
qemu-riscv ML.

On 4/9/24 03:29, Jason Chien wrote:
> Ping.
>
> Jason Chien <jason.chien@sifive.com <mailto:jason.chien@sifive.com>> 於 
> 2024年3月28日 週四 上午10:23寫道：
>
>     This patch series adds the support for Zve32x and Zvx64x and makes vector
>     registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
>     v2:
>          Rebase onto riscv-to-apply.next (commit 385e575).
>     v3:
>          Spuash patch 2 into patch 1.
>          Spuash patch 4 into patch 3.
>
>     Jason Chien (3):
>        target/riscv: Add support for Zve32x extension
>        target/riscv: Add support for Zve64x extension
>        target/riscv: Relax vector register check in RISCV gdbstub
>
>       target/riscv/cpu.c                      |  4 +++
>       target/riscv/cpu_cfg.h                  |  2 ++
>       target/riscv/cpu_helper.c               |  2 +-
>       target/riscv/csr.c                      |  2 +-
>       target/riscv/gdbstub.c                  |  2 +-
>       target/riscv/insn_trans/trans_rvv.c.inc |  4 +--
>       target/riscv/tcg/tcg-cpu.c              | 33 ++++++++++++++-----------
>       7 files changed, 30 insertions(+), 19 deletions(-)
>
>     -- 
>     2.43.2