qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH 65/65] target/riscv: Enable XTheadVector extension for c906


From: Huang Tao
Subject: [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906
Date: Fri, 12 Apr 2024 15:37:35 +0800

This patch enables XTheadVector for the c906.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 05652e8c87..e85aa51237 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -542,7 +542,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.ext_xtheadmemidx = true;
     cpu->cfg.ext_xtheadmempair = true;
     cpu->cfg.ext_xtheadsync = true;
-    cpu->cfg.ext_xtheadvector = false;
+    cpu->cfg.ext_xtheadvector = true;
 
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
-- 
2.44.0




reply via email to

[Prev in Thread] Current Thread [Next in Thread]