Re: [PATCH] Fix incorrect disassembly format for certain RISC-V instructions

[Michael Tokarev]

03.04.2024 12:14, Simeon Krastnikov wrote:
> * The immediate argument to lui/auipc should be an integer in the interval
>   [0x0, 0xfffff]; e.g., 'auipc 0xfffff' and not 'auipc -1'
> * The floating-point rounding mode is the last operand to the function,
>    not the first; e.g., 'fcvt.w.s a0, fa0, rtz' and not 'fcvt.w.s rtz,
> a0, fa0'. Note that fcvt.d.w[u] and fcvt.w[u].d are unaffected by the
> rounding mode and hence it is omitted from their disassembly.
> * When aq and rl are both present, they are not separated by a '.';
>    e.g., 'lr.d.aqrl' and not 'lr.d.aq.rl'.
>
> Based on the following assembly reference:
> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md

Can someone from the riscv team review this?

This change isn't "trivial enough" for qemu-trivial, it should be picked up
by the riscv team.  At the very least, it touches too many instructions.

Thanks,

/mjt