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[PULL 11/14] target/xtensa: Assert that interrupt level is within bounds
From: |
Peter Maydell |
Subject: |
[PULL 11/14] target/xtensa: Assert that interrupt level is within bounds |
Date: |
Thu, 6 Jul 2023 14:25:09 +0100 |
In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
complains about a possible array overrun (CID 1507131)
Add an assert() which will make Coverity happy and catch the unlikely
case of a mis-set XCHAL_NUM_INTLEVELS in future.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
---
target/xtensa/exc_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
index d4823a65cda..43f6a862de2 100644
--- a/target/xtensa/exc_helper.c
+++ b/target/xtensa/exc_helper.c
@@ -169,6 +169,9 @@ static void handle_interrupt(CPUXtensaState *env)
CPUState *cs = env_cpu(env);
if (level > 1) {
+ /* env->config->nlevel check should have ensured this */
+ assert(level < sizeof(env->config->interrupt_vector));
+
env->sregs[EPC1 + level - 1] = env->pc;
env->sregs[EPS2 + level - 2] = env->sregs[PS];
env->sregs[PS] =
--
2.34.1
- [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance, (continued)
- [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance, Peter Maydell, 2023/07/06
- [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues, Peter Maydell, 2023/07/06
- [PULL 13/14] target/arm: Define neoverse-v1, Peter Maydell, 2023/07/06
- [PULL 06/14] target/arm: Fix SME full tile indexing, Peter Maydell, 2023/07/06
- [PULL 10/14] hw: arm: allwinner-sramc: Set class_size, Peter Maydell, 2023/07/06
- [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG, Peter Maydell, 2023/07/06
- [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers, Peter Maydell, 2023/07/06
- [PULL 05/14] target/arm: Dump ZA[] when active, Peter Maydell, 2023/07/06
- [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs, Peter Maydell, 2023/07/06
- [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1, Peter Maydell, 2023/07/06
- [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds,
Peter Maydell <=
- [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump, Peter Maydell, 2023/07/06
- [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case, Peter Maydell, 2023/07/06
- Re: [PULL v2 00/14] target-arm queue, Richard Henderson, 2023/07/06