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[PATCH v4 37/48] target/loongarch: Implement xvfrstp
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From: |
Song Gao |
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Subject: |
[PATCH v4 37/48] target/loongarch: Implement xvfrstp |
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Date: |
Wed, 30 Aug 2023 16:48:51 +0800 |
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/insns.decode | 5 ++
target/loongarch/disas.c | 5 ++
target/loongarch/vec_helper.c | 48 ++++++++++++--------
target/loongarch/insn_trans/trans_lasx.c.inc | 5 ++
4 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index cb6db8002a..6035fe139c 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1811,6 +1811,11 @@ xvbitrevi_h 0111 01110001 10000 1 .... ..... .....
@vv_ui4
xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5
xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6
+xvfrstp_b 0111 01010010 10110 ..... ..... ..... @vvv
+xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv
+xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5
+xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index dad9243fd7..27d6252686 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2235,6 +2235,11 @@ INSN_LASX(xvbitrevi_h, vv_i)
INSN_LASX(xvbitrevi_w, vv_i)
INSN_LASX(xvbitrevi_d, vv_i)
+INSN_LASX(xvfrstp_b, vvv)
+INSN_LASX(xvfrstp_h, vvv)
+INSN_LASX(xvfrstpi_b, vv_i)
+INSN_LASX(xvfrstpi_h, vv_i)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c
index 03b42dc887..5c53cc8962 100644
--- a/target/loongarch/vec_helper.c
+++ b/target/loongarch/vec_helper.c
@@ -2251,37 +2251,45 @@ DO_BITI(vbitrevi_d, 64, UD, DO_BITREV)
#define VFRSTP(NAME, BIT, MASK, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
- int i, m; \
+ int i, j, m, ofs; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
+ int oprsz = simd_oprsz(desc); \
\
- for (i = 0; i < LSX_LEN/BIT; i++) { \
- if (Vj->E(i) < 0) { \
- break; \
+ ofs = LSX_LEN / BIT; \
+ for (i = 0; i < oprsz / 16; i++) { \
+ m = Vk->E(i * ofs) & MASK; \
+ for (j = 0; j < ofs; j++) { \
+ if (Vj->E(j + ofs * i) < 0) { \
+ break; \
+ } \
} \
+ Vd->E(m + i * ofs) = j; \
} \
- m = Vk->E(0) & MASK; \
- Vd->E(m) = i; \
}
VFRSTP(vfrstp_b, 8, 0xf, B)
VFRSTP(vfrstp_h, 16, 0x7, H)
-#define VFRSTPI(NAME, BIT, E) \
-void HELPER(NAME)(void *vd, void vj, uint64_t imm, uint32_t desc) \
-{ \
- int i, m; \
- VReg *Vd = (VReg *)vd; \
- VReg *Vj = (VReg *)vj; \
- \
- for (i = 0; i < LSX_LEN/BIT; i++) { \
- if (Vj->E(i) < 0) { \
- break; \
- } \
- } \
- m = imm % (LSX_LEN/BIT); \
- Vd->E(m) = i; \
+#define VFRSTPI(NAME, BIT, E) \
+void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
+{ \
+ int i, j, m, ofs; \
+ VReg *Vd = (VReg *)vd; \
+ VReg *Vj = (VReg *)vj; \
+ int oprsz = simd_oprsz(desc); \
+ \
+ ofs = LSX_LEN / BIT; \
+ m = imm % ofs; \
+ for (i = 0; i < oprsz / 16; i++) { \
+ for (j = 0; j < ofs; j++) { \
+ if (Vj->E(j + ofs * i) < 0) { \
+ break; \
+ } \
+ } \
+ Vd->E(m + i * ofs) = j; \
+ } \
}
VFRSTPI(vfrstpi_b, 8, B)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 92c6506e04..8a7d1b41e1 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -560,6 +560,11 @@ TRANS(xvbitrevi_h, LASX, gvec_vv_i, 32, MO_16, do_vbitrevi)
TRANS(xvbitrevi_w, LASX, gvec_vv_i, 32, MO_32, do_vbitrevi)
TRANS(xvbitrevi_d, LASX, gvec_vv_i, 32, MO_64, do_vbitrevi)
+TRANS(xvfrstp_b, LASX, gen_vvv, 32, gen_helper_vfrstp_b)
+TRANS(xvfrstp_h, LASX, gen_vvv, 32, gen_helper_vfrstp_h)
+TRANS(xvfrstpi_b, LASX, gen_vv_i, 32, gen_helper_vfrstpi_b)
+TRANS(xvfrstpi_h, LASX, gen_vv_i, 32, gen_helper_vfrstpi_h)
+
TRANS(xvreplgr2vr_b, LASX, gvec_dup, 32, MO_8)
TRANS(xvreplgr2vr_h, LASX, gvec_dup, 32, MO_16)
TRANS(xvreplgr2vr_w, LASX, gvec_dup, 32, MO_32)
--
2.39.1
- [PATCH v4 33/48] target/loongarch: Implement xvssrlrn xvssrarn, (continued)
- [PATCH v4 33/48] target/loongarch: Implement xvssrlrn xvssrarn, Song Gao, 2023/08/30
- [PATCH v4 34/48] target/loongarch: Implement xvclo xvclz, Song Gao, 2023/08/30
- [PATCH v4 38/48] target/loongarch: Implement LASX fpu arith instructions, Song Gao, 2023/08/30
- [PATCH v4 42/48] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/08/30
- [PATCH v4 39/48] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/08/30
- [PATCH v4 37/48] target/loongarch: Implement xvfrstp,
Song Gao <=
- [PATCH v4 40/48] target/loongarch: Implement xvseq xvsle xvslt, Song Gao, 2023/08/30
- [PATCH v4 43/48] target/loongarch: Implement xvinsgr2vr xvpickve2gr, Song Gao, 2023/08/30
- [PATCH v4 44/48] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v, Song Gao, 2023/08/30
- [PATCH v4 47/48] target/loongarch: Implement xvld xvst, Song Gao, 2023/08/30
- [PATCH v4 45/48] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/08/30
- [PATCH v4 14/48] target/loongarch: Implement xvabsd, Song Gao, 2023/08/30
- [PATCH v4 46/48] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins, Song Gao, 2023/08/30