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[PULL 12/57] target/loongarch: Rename MMU_IDX_*
From: |
Richard Henderson |
Subject: |
[PULL 12/57] target/loongarch: Rename MMU_IDX_* |
Date: |
Fri, 2 Feb 2024 15:49:51 +1000 |
The expected form is MMU_FOO_IDX, not MMU_IDX_FOO.
Rename to match generic code.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.h | 8 ++++----
target/loongarch/cpu.c | 2 +-
target/loongarch/tcg/tlb_helper.c | 4 ++--
target/loongarch/tcg/translate.c | 2 +-
target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +-
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 5dfcfeb3a4..47fd110e81 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -404,15 +404,15 @@ struct LoongArchCPUClass {
*/
#define MMU_PLV_KERNEL 0
#define MMU_PLV_USER 3
-#define MMU_IDX_KERNEL MMU_PLV_KERNEL
-#define MMU_IDX_USER MMU_PLV_USER
-#define MMU_IDX_DA 4
+#define MMU_KERNEL_IDX MMU_PLV_KERNEL
+#define MMU_USER_IDX MMU_PLV_USER
+#define MMU_DA_IDX 4
int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
- return MMU_IDX_USER;
+ return MMU_USER_IDX;
#else
return loongarch_cpu_mmu_index(env_cpu(env), ifetch);
#endif
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index cbecc63213..139acfe373 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
}
- return MMU_IDX_DA;
+ return MMU_DA_IDX;
}
static void loongarch_la464_initfn(Object *obj)
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_helper.c
index 449043c68b..65ffbef08e 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -188,8 +188,8 @@ static int get_physical_address(CPULoongArchState *env,
hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
- int user_mode = mmu_idx == MMU_IDX_USER;
- int kernel_mode = mmu_idx == MMU_IDX_KERNEL;
+ int user_mode = mmu_idx == MMU_USER_IDX;
+ int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
uint32_t plv, base_c, base_v;
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 235515c629..58674cb268 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -125,7 +125,7 @@ static void
loongarch_tr_init_disas_context(DisasContextBase *dcbase,
if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
ctx->mem_idx = ctx->plv;
} else {
- ctx->mem_idx = MMU_IDX_DA;
+ ctx->mem_idx = MMU_DA_IDX;
}
/* Bound the number of insns to execute to those left on the page. */
diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
index 01d457212b..7e4ec93edb 100644
--- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc
@@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
static void check_mmu_idx(DisasContext *ctx)
{
- if (ctx->mem_idx != MMU_IDX_DA) {
+ if (ctx->mem_idx != MMU_DA_IDX) {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
}
--
2.34.1
- [PULL 02/57] target/alpha: Split out alpha_env_mmu_index, (continued)
- [PULL 02/57] target/alpha: Split out alpha_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 03/57] target/alpha: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 04/57] target/arm: Split out arm_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 05/57] target/arm: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 06/57] target/avr: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 07/57] target/cris: Cache mem_index in DisasContext, Richard Henderson, 2024/02/02
- [PULL 08/57] target/cris: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 09/57] target/hppa: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 10/57] target/i386: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 11/57] target/loongarch: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 12/57] target/loongarch: Rename MMU_IDX_*,
Richard Henderson <=
- [PULL 13/57] target/m68k: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 14/57] target/microblaze: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 15/57] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill, Richard Henderson, 2024/02/02
- [PULL 19/57] target/openrisc: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 20/57] target/ppc: Split out ppc_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 21/57] target/ppc: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 22/57] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 18/57] target/nios2: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 17/57] target/mips: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 16/57] target/mips: Split out mips_env_mmu_index, Richard Henderson, 2024/02/02