Re: [avr-chat] MEGA vs XMEGA core differences?

[Rick Mann]

Thanks, Thomas, that's very helpful. Someone else succeeded in making the port 
work under the IAR compiler, but I haven't talked to him yet about what he did.

Given that the only interrupt I'm currently servicing is the scheduler 
interrupt, RETI should be enough to restore the PMIC state, right?

Moreover, is per-thread PMIC state the right thing to do? It seems to me that 
interrupts are independent of threads, and so the state should be identical 
after each handler returns, regardless of whether or not a new thread is 
executing afterward, right?


On Apr 28, 2013, at 00:19 , "Thomas D. Dean" <address@hidden> wrote:

> On 04/27/13 23:12, Rick Mann wrote:
>> So, I'm sitting here trying to port ChibiOS to XMEGA. It runs well on 
>> something like an ATmega128.
>> 
> 
> In the ATmega 128,
> 
> When an interrupt occurs, the Global Interrupt Enable I-bit is cleared
> and all interrupts are disabled. The user software can write logic one
> to the I-bit to enable nested interrupts. All enabled interrupts can
> then interrupt the current interrupt routine. The I-bit is
> automatically set when a Return from Interrupt instruction ­ RETI ­ is
> executed.
> 
> If you are using ret, you must set the Global Interrupt Enable I-bit in the 
> code, if you want interrupts enabled.  Of course, a context switch should 
> result in a possibly new SREG.
> 
> For the xmega,
> 
> SREG:
> The Global Interrupt Enable bit must be set for interrupts to be enabled. If 
> the Global Interrupt Enable Register is cleared, none of the interrupts are 
> enabled independent of the individual interrupt enable settings. The I-bit is 
> not cleared by hardware after an interrupt has occurred.  The I-bit can be 
> set and cleared by the application with the SEI and CLI instructions, as 
> described in the "Instruction Set Description".
> 
> PMIC:
> When an interrupt is enabled and the interrupt condition is present, the PMIC 
> will receive the interrupt request. Based on the interrupt level and 
> interrupt priority of any ongoing interrupts, the interrupt is either 
> acknowledged or kept pending until it has priority.  When the interrupt 
> request is acknowledged, the program counter is updated to point to the 
> interrupt vector. The interrupt vector is normally a jump to the interrupt 
> handler; the software routine that handles the interrupt.
> After returning from the interrupt handler, program execution continues from 
> where it was before the interrupt occurred. One instruction is always 
> executed before any pending interrupt is served.
> 
> The PMIC status register contains state information that ensures that the 
> PMIC returns to the correct interrupt level when the RETI (interrupt return) 
> instruction is executed at the end of an interrupt handler. Returning from an 
> interrupt will return the PMIC to the state it had before entering the 
> interrupt. The Status Register (SREG) is not saved automatically upon an 
> interrupt request. The RET (subroutine return) instruction cannot be used 
> when returning from the interrupt handler routine, as this will not return 
> the PMIC to its right state.
> 
> This is more complicated.  You have to make sure the PMIC is set to the 
> correct state.  Maybe save and restore the the PMIC Status Register.
> 
> There may be other things???
> 
> Tom Dean


-- 
Rick