[Bug binutils/19921] New: enable specification of data width when writing verilog hex format

[jamey.hicks at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=19921

            Bug ID: 19921
           Summary: enable specification of data width when writing
                    verilog hex format
           Product: binutils
           Version: 2.27 (HEAD)
            Status: NEW
          Severity: enhancement
          Priority: P2
         Component: binutils
          Assignee: unassigned at sourceware dot org
          Reporter: jamey.hicks at gmail dot com
  Target Milestone: ---

Verilog $readmemh is rather limited and reads one array value per white-space
separated number. In order to read into a 32-bit or 64-bit array, the data must
be formatted accordingly.

I propose to modify the verilog target in order to add data width
specification. I see several ways to go about this:

 * define verilog16, verilog32, and verilog64 targets, so that the target
specifies the data width
 * default to the data width of the architecture
 * add options to object copy similar to srec-len.

The first option is the most flexible, but I'm looking for the option that
binutils maintainers would be willing to accept.

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