[Bug binutils/19921] enable specification of data width when writing verilog hex format

[olof.kindgren at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=19921

Olof Kindgren <olof.kindgren at gmail dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |olof.kindgren at gmail dot com

--- Comment #4 from Olof Kindgren <olof.kindgren at gmail dot com> ---
This works fine, but the byte ordering caused by "for (i = VerilogDataWidth-1;
i >= 0; i--)" is a bit unexpected, at least on OpenRISC. I'm not sure yet if we
need to change the ordering only on BE targets, or if should be reversed on
both LE and BE targets

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