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[Bug binutils/24739] RISC-V Disassembler should default to little endian

From: cvs-commit at gcc dot gnu.org
Subject: [Bug binutils/24739] RISC-V Disassembler should default to little endian
Date: Thu, 27 Jun 2019 00:18:37 +0000


--- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Jim Wilson <address@hidden>:


commit d7560e2df501c7da1b0e4e64116dd52fe5715a96
Author: Jim Wilson <address@hidden>
Date:   Wed Jun 26 17:17:09 2019 -0700

    RISC-V: Make objdump disassembly work right for binary files.

    Without the ELF header to set info->endian, it ends up as
    which gets printed as big-endian.  But RISC-V instructions are always
    endian, so we can set endian_code correctly, and then set display_endian
    that.  This is similar to how the aarch64 support works, but without the
    support for constant pools, as we don't have that on RISC-V.

        PR binutils/24739
        * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
        Set info->display_endian to info->endian_code.

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