Re: still some trouble with busses

[Steven Rubin]

> Thanks for the note, Steve. Here is what I did:
>
> 1: Open a new facet. Draw an invertor with en export on the input
> called 'in' and an export on the output called 'out'.
> 2: View -> Make ICON view
> 3: Open a new facet. Place the icon created previously. Double click
> it and give it the name 'buftest[3:0]'.
> 4. Extend a type input bus from from the input. Create an export for it called
> 'input[3:0]'.
> 5: Extend a type output bus from the output. Create an export for it called
> 'output[3:0]'.

So far, so good.

> 6: Place an AND gate and an XOR gate. I can't seem to get pins to
> connect to busses without ripping so I did rip it. I connected all
> outputs (output[3], output[2], output[1] and output[0] to the gates -
> two per.
> 7. For the heck of it, created exports called ANDOUT and XOROUT where
> appropriate.

I see trouble here.  IRSIM doesn't know about the logic gates in the 
Digital Schematics technology.  You have to create you own "and" and "or" 
circuits out of transistors.

> I set IRSIM as the simulator and told it to simulate. Here is the
> output:
> > vector  input[3] input[2] input[1] input[0]
> ((null),0): cannot find node input[2]
> ((null),0): cannot find node input[1]
> ((null),0): cannot find node input[0]

One good way to debug the IRSIM interface is to use the "Tools / Simulation 
(Others) / Write IRSIM Deck" command to explicitly generate the IRSIM 
netlist.  Then look at the file.  Because the AND gate was not understood, 
the input to it was probably ignored from the netlist.  Thus the simulator 
has no knowledge of those nodes.

   -Steven Rubin