Electric and TSMC0.18

[YunleSun]

Hi all,

 

I'm learning to make layouts in Electric for TSMC 0.18 Micron Process. I'm using the

SCMOS_DEEP rules (with lambda of 0.09). Some of the design rules are:

1. Contact size is 0.18 umX 0.18 um (i.e. 2 lmbdaX 2 lmbda);
2. Width of device (minimum) is 0.27um (i.e. 3 lmbda);
3. Aspace space  (minimum) is 0.27 um (i.e. 3 lmbda);
4. Poly to active space (minimum) is 0.09um (i.e. 1 lmbda).

I find they are different from the ones in TSMC0.18 rules (in Cadence), where:

1. Contact size is 0.22 umX 0.22 um;
2. Width of device (minimum) is 0.22um;
3. Aspace space  (minimum) is 0. 28um;
4. Poly to active space (minimum) is 0.10um.

I tried exporting the GDSII files and LEF files from Electric (SCMOS_DEEP) and then importing them

into Cadence (TSMC0.18).  I failed to transfer them because of the differences metioned above. I got

DRC errors in Cadence although DRC passed in Electric. What can I do with the DRC errors in Cadence? 

Is it possible to make layouts in Electric for TSMC 0.18 Process and then transfer them into Cadence

without errors? If yes, which technology (and options) is better in Electric? If not,  I should try making up

a dedicated TSMC 0.18 technology in Electric, although I think it is not easy. 

 

Regards,

 

Yunle Sun