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Thanks Steven.
I find there are two sets of MOSIS CMOS design
rules for TSMC 0.18 Micron Process:
- SCN6M_SUBM.
lambda: 0.10 um. Minimum width of gate: 0.20 um (= 0.10 um X
2).
- SCN6M_DEEP.
lambda: 0.09 um. Minimum width of gate: 0.18um (= 0.09
um X 2).
Did you mean that I have to make the gate
size 0.2 even if I use SCN6M_DEEP in Electric?
If anybody else has the experience, please let me
know.
Regards,
Yunle Sun
It isn't an
issue of Electric vs. Cadence. Rather, it is a question of which
fabrication house you are going to use. When MOSIS tells you that they
are using a 0.18 process, they still ask you to make the gate size 0.2 because
they are going to compensate your geometry down to 0.18 before
fabrication. Actually, MOSIS CMOS is able to target many different fab
houses, not just TSMC. So their geometries are more general.
Both
Electric and Cadence are willing to draw geometries at any size, but they have
to target the same design rule specifications. Electric's MOSIS CMOS
design rules consider everything to be relative to the 0.2 sizes. Does
Cadence? If not, this explains the trouble.
If you want to scale
your Electric designs, you can change the value of lambda before writing
GDS. Then you can get it into Cadence. But there will surely be
small differences in the design rules that still require
hand-editing.
-Steven Rubin
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