I have created a schematic that has a 2-bit bus for input and two
single wires for output. The bus is ripped and the lines are sent
through two buffers to the output wires. The VHDL is correct and
this circuit will run through the ALS simulator in Electric 8.02.
I then created an IC for this circuit and placed it in another schematic.
The new schematic has a 2-bit bus input export and two wire output
exports. These exports are mapped to the input and output ports of
the IC.
The call to the IC in the VHDL is incorrect. The network name is incorrect.
It reads A_1_0 twice instead of A_1_ and A_0_. The port is not recognized
as it should, it is labeled as 'open'.
There is no network named A_1_0_ in the cells.
This seems to be a problem with the VHDL generator.
I have attached the jelib that has this example in it.
Here is the VHDL that is generated:
-- VHDL automatically generated from cell 'call_split{sch}'
entity call_split is port(A_1_, A_0_: in BIT; D0, D1: out BIT);
end call_split;
architecture call_split_BODY of call_split is
component split port(A_1_0_, A_1_0_: in BIT; D0, D1: out BIT);
end component;