Re: [Discuss-gnuradio] Re: synchronizing sound cards in a cluster

[Eric Blossom]

On Fri, Mar 14, 2003 at 01:35:08AM -0500, Dave Emery wrote:
> On Thu, Mar 13, 2003 at 09:23:23PM -0800, Eric Blossom wrote:
> > 
> > If you want to run the converters at full speed, I don't think you're
> > going to get external trigger:
> > 
> >   (1) The on board oscillator is 120 MHz.  Clock jitter needs to be
> >       held to single digit picoseconds for us to be able to
> >       successfully IF sample.
> 
>       Absolutely.   I was thinking you were going after something
> somewhat slower.   But yes, you do need a low jitter clock to work
> with IF sampling and narrow bandwidth signals.
> 
>       It sure would be nice to be able to use a 120 mhz 
> high stability xtal vco which could be narrow loop bandwidth phase
> locked to a 10 mhz reference.   This kind of technology is widely
> used now in synthesizers for critical phase noise applications like
> microwave spectrum analyzer LOs where the phase noise (and jitter)
> is primarily that of the hf xtal VCO outside of the loop bandwidth
> which can be made rather narrow.
> 
> 
> 
> >   (2) If we were to accept a 10 MHz timing reference, we'd need to
> >       multiply it a bunch of times, and then get the jitter worked
> >       out of it.  Not easy to do.
> 
>       I realize that cost is the big killer here.   Again I'm not
> talking about directly using a harmonic of a supplied 10 mhz but 
> extremely narrowband phase locking of a 120 mhz high stability xtal VCO
> to the 10 mhz reference.   This can be done with a straightforward PLL I
> should think.   I know there are 120 mhz region low jitter canned xtal
> clock oscillators with frequency control inputs around and the rest is
> very straightforward.

Thanks for explaining this.  We've talked about possibly doing a
higher cost, more full featured PCI board (don't hold your breath).
This would be a candidate for that design.

> 
>       Any idea at all of SFDR or where your intermodulation floor
> might be with any of the chips being considered ?   And any idea
> of what the analog front end might look like (AGC ?  Signal levels ?)

The two A/D's were looking at are the

AD9218-65 dual 10-bit 65 MHz:
    
    SFDR 68 dBc (to Nyquist)
    budgetary price $12


AD9238-65 dual 12-bit 65 MHz:

    SFDR 85 dBc (to Nyquist)
    budgetary price $28


Both of these parts take either  1V p-p or a 2V p-p inputs.

There will be no AGC on the board.  We're trying for a minimal, but
general solution to solving the problem of getting the samples into
and out of the PC.  Philosophically this is "extreme programming" for
hardware.  "What's the simplest thing that could possibly work?"  
We're leaving signal conditioning, filtering, AGC and xverters for other
boards that we expect someone else to design and build.

>       And will there be Gnu VHDL or equivalent open source tool chains
> for the FPGA available or how will those who don't want to just use
> the canned versions of the FPGA code get access to low cost tools 
> to develop their own code ?

We've got our eye on this too.  Some kind of no-cost tools will be
used.  Assuming we end up using Xilinx, we'll probably initially use
their free (beer) tools available on their web site.  They'll work
with parts up to the 300K gate Spartan IIE's we're thinking about.
One down side is that they only run on a non-free operating system.

We are also investigating a completely free (liberty) tool path.  As I
understand the situation, there are still some holes in the path that
need to be filled in.  If there are any "Free EDA" guys lurking,
perhaps we could start a discussion on the Wiki about this, or at
least link to other sites where this is being hashed out.

see:
        http://comsec.com/wiki?FieldProgrammableGateArray
        http://comsec.com/wiki?FpgaToolChain

Eric