Re: [Discuss-gnuradio] USB2 <-> fast ADC & DAC

[Joseph DiVerdi]

Dear Andy,

<snip>
>Its easy enough to cut down the sample rate, the difficult choice is 
>in deciding which ADC/DAC to use so that its cheap enough for 
>'slower' uses like yours but fast enough to capture data from the 
>most desirable uses.
>
>What is the minimum resolution your application can live with?
<snip>

Based on the signal processing I expect to do to the data I could probably live 
with 10-bit resolution but must admit some reluctance to going that low. I 
suspect that many applications can survive, or even succeed, on lower 
resolution than the designer is willing to specify. 

<snip>
>10.7MHz IF seems to have been discussed a lot.  This is unfortunately 
>a lot of data, in quadrature at 12 bit resolution it is 
>32.1MBytes/sec.  We can look an USB2 Isochronous mode which can 
>probably cope with this throughput, although I understand that PCI 
>bugs start to surface in some chipsets if you push your luck with the 
>throughput.  Its a lot of data for the CPU to process in a meaningful 
>way in realtime.  Has anyone else looked at attempting this at that 
>datarate?
<snip>

Here is where there may be a significant gain available through undersampling. 
Please remember the Nyquist sampling requirement doesn't specify "...twice the 
highest frequency that must be resolved..." but rather "...twice the bandwidth 
that must be resolved..." (please excuse the paraphrasing and any mis-quoting). 

If the IF signal to be captured is centered at 10.7MHz with a full bandwidth of 
2MHz (+/-1MHz) then only a 4MSample/second acquisition rate is required not 
23.4MSample/second ((10.7 + 1) * 2). The front end amplifier and track/hold 
devices must operate at the highest frequency but the ADC need not sample that 
high.

If the IF signal to be captured is centered at 10.7MHz with a full bandwidth of 
10MHz (+/-5MHz) then a 20MSample/second acquisition rate is required not 
31.4MSample/second ((10.7 + 5) * 2). 

<snip>
>Just the kind of advice I am looking for, thank you.
<snip>

Happy to help.

BTW, some applications will require that the data be sampled by the ADCs at a 
specific time, that is, will require an external sampling clock. It isn't just 
a matter of the sampling rate being controlled externally, rather it is rate 
and phase or exact time in a sequence of events, etc. I strongly suggest that 
this capability be selectably/optionally included. Of course, with a 
differential clock input. ;)

>- -Andy

One more system architecture thought: I have been involved in large-scale 
projects which were intended, at the outset, to be incredibly general purpose, 
so much so that a design value was articulated that went something like this 
"...it's got to be able to do anything we can think of plus anything we haven't 
thought of..." It may seem humorous now but the speaker was deadly serious at 
the time. I throw this out because of your stated desire to be "completely 
generic" and the fear that someone will hold you to it. ;)

Best regards,
Joseph
-- 
Joseph A. DiVerdi, Ph.D., M.B.A.          
http://xtrsystems.com/           970.980.5868 (voice) 
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