David Bengtson wrote:
Martin Dvh wrote:
Why don't you use the usrp to generate your 16.384 or 32.768 MHz
refclock. Most daugterboards (except the tvrx) use this feature
(They all use a 4Mhz refclock on io pin 0. The only difference
with your design is that you need another frequency. The cyclone
fpga in the usrp has internal PLLs which can generate all kinds
of frequencies. (They are not used at the moment)
(Sorry, there is a typo, the reference frequencies are
16.368/32.736 MHz) That might work. 16.368 MHz/4 MHz is 1023/250,
or a comparison frequency of 16 kHz. From a frequency generation
point of view, I could probably get the right frequency from the
USRP I'm concerned about jitter and noise on that line though. The
reference is used directly for the comparison frequency in the
on-chip PLL, to generate a LO that is 1571.328 MHz. A 16 kHz
The generation of 1571.328 from this source is almost surely a deal
killer because of the phase noise. That LO must be accurate,
stable, and as phase noise free as possible. We are trying to work
with a signal of only a few dB dynamic range signal and it is weak,
right at the noise floor in most systems. Cascaded LNA's will bring
the signal up but also lower the IP3 and the dynamic range and
greatly increase the front end susceptibility to overload,
interference, and collapse. This particular oscillator and the
attendant mixer cannot be scrimped on. At least do a serious noise
budget analysis to make sure the system will actually be usable after
built.