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Re: [Discuss-gnuradio] FPGA bit file -- again


From: Angilberto Muniz Sb
Subject: Re: [Discuss-gnuradio] FPGA bit file -- again
Date: Mon, 29 May 2006 06:55:28 -0700 (PDT)

Thank you, Amit.

You're correct -- "ddc.v" is not used, the right stuff
is in "rc_chain.v" file.

Now the next step...

Regards,

Angilberto.

--- amit malani <address@hidden> wrote:

> to the extend of my knowledge, i guess ddc.v is not
> used.
> 
> give a look to the rx_chain.v file,  you will find
> cic_decim.v and
> halfband_decim.v being used in that. all files are
> in usrp/fpga/std_lib.
> 
> if you are using quartus then you may give a try to
> the RTL viewer in Tools
> once you open the project from
> usrp/fpga/toplevel/usrp_std i.e. the
> usrp_std.qpf file.....it will ease you work on
> locating what is used and
> where....
> 
> and by the time you get real help, i hope you can
> survive with this one ;)
> 
> regards,
> amit
> 
> On 5/28/06, Angilberto Muniz Sb
> <address@hidden> wrote:
> >
> > I guess my message got into a black hole :-)
> >
> > Anyone has an idea where I can find the files
> > "cic_inter_2stage.v" and "cic_decim_2stage.v" ??
> >
> > As we can see, they are referenced on the "ddc.v"
> > file:
> >
> > cic_decim_2stage #(.bw(bw),.N(4))
> >                
> decim_i(.clock(clock),.reset(reset),.enable(enable),
> >
> >
> >
>
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
> >                        
> .signal_in(i_cordic_out),.signal_out(i_out));
> >
> >
> > Or if they doesnt exist at all, it means the
> "ddc.v"
> > code is never compiled? If so, how come we have
> 1,2 or
> > 4 DDC in the system?
> >
> > Thankx,
> >
> > Angilberto.
> >
> >
> > ==============================
> > From:  Angilberto Muniz Sb
> > Subject:  [Discuss-gnuradio] FPGA bit file --
> again
> > Date:  Mon, 12 Dec 2005 16:46:05 -0800 (PST)
> >
> >
> >
>
--------------------------------------------------------------------------------
> >
> > I'm trying to bypass the hardware DDC/DUC and
> tying to
> > implement the FPGA based UP/DOWN conveters.
> >
> > Looking into 'ddc.v' and 'duc.v' we see references
> to
> > 'cic_decim_2stage' and 'cic_interp_2stage'
> > respectively, but there are no '.v' equivalent
> files
> > -- the close to it are 'cic_interp.v' and
> > 'cic_decim.v' --
> >
> > I assume the '_2state' refers to '2nd stage
> decimating
> > and interpolating' -- Am I right?
> >
> > Is it just tipo error? If so, how come I get no
> error
> > compiling the project under Quartus?
> >
> > Thank you,
> >
> > Angilberto.
> >
> >
> >
> > __________________________________________________
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> >
>
http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
> >
> 
> 
> 
> -- 
> Amit Malani
> Master of Science (Information Networking)
> Carnegie Mellon University
> mobile: 001 516 209 1358
> 


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