Hello, I would like to recompile all the verilog files for the FPGA in order to have a better understanding of the role of each module. I believe the program used to compile the files was Quartus II. Is that correct?
Also, i know that Xilinx ISE can give an RTL schematic of the whole design once it is synthesized. That could be very helpful for me to see all the inter connections between the different verilog modules. Does Quartus II have such a feature?
If it does, can Quartus II run on a Linux platform (I am running Ubuntu)?