I have a narrowband FM receiver running (not based on GNU radio) using the usrp library and the USRP hardware. I would be helpful if the USRP firmware could reduce the sample to 25 ksps from the current 250 ksps at the maximum decimation factor. I want to try run ning my FM receiver on a TI OSK board so reducing the data rate would be very helpful.
I am pretty sure I can reduce the ADC sample rate by half, would it be possible to get some additional decimation from teh FPGA image? I am not much of an FPGA guy unfortunately.