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Re: [Discuss-gnuradio] Regarding programming the fpga


From: Brian Padalino
Subject: Re: [Discuss-gnuradio] Regarding programming the fpga
Date: Fri, 2 Mar 2007 11:17:19 -0500

On 3/2/07, Kuntal Majumdar <address@hidden> wrote:

Ok,
My project aims at programming the fpga as a fft-ifft block, but i am a
complete novice to the usrp, so as a basic first step, all i am trying to
accomplish is that i program the fpga as a simple 4-bit counter and take in
the data. I already have a code written ccs which works upon this data and
gives me results which help me on my work further. But till date, I was
using a signal generator to feed data to the DSK, but now, I want the fpga
to do the same. Once programmed, it should feed the DSK with data, so for
starters, I want to program it as a simple counter. Later, I want to model
the fpga as a fft-ifft block, which does the fft-ifft as required on being
fed by the data from the DSK. This is what I am aiming at.

Have you written an FFT-IFFT block in Verilog yet?  I don't know what
CCS is - you will have to enlighten me.

You should do all this inside a simulation first before trying to
accomplish it in the actual hardware.  Do you know how to write a
testbench in Verilog?

So, after building the radio, i tried running the sample examples as given
and they ran perfectly. So,
Brian, do u now intend to tell me that I should I try Matt's usrp_std and
program the fpga with that. Even if I do that, how do I assign the pins for
the fpga, I mean, the external IO pins. Or is there any relevant
documentation on this anywhere?

The external IO pins should not have to be mapped if you use Matt's
Quartus II project.  It will already have the pins mapped to where
they have to be mapped.

When you insert your FFT-IFFT, you should just instantiate your module
within the pipeline somewhere.  That pipeline is somewhat described
here:

   http://gnuradio.org/trac/wiki/UsrpFPGA

As a side note - GNURadio can process FFT and IFFT on the host side as
it is - is there a reason you're doing the FFT and IFFT within the
FPGA instead?

Thanks a lot for the support.

Regards,
Kuntal

Brian




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