There's a header file:
GNU_Radio\usrp\fpga\toplevel\usrp_std\config.vh
That header controls the build configuration and is now functional.
Modify it to use the file:
GNU_Radio\usrp\fpga\toplevel\include\common_config_1rxhb_1tx.vh
This is how:
// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit
channel
`include "../include/common_config_1rxhb_1tx.vh"
This will free up alot of space on the fpga for experimentation!
Lee Studley
Embedded SW/HW Eng.
Kutta Consulting, Inc.
www.kuttaconsulting.com
At 03:02 PM 9/5/2007, S Mande wrote:
Hi,
I am trying to add some functionalities to the existing FPGA in
USRP.
I went through the mailing list and figured out that the current
Verilog/VHDL code implementation occupies 90% of FPGA's resources.
However, there were some mails that pointed that reducing some reveiver
functionalities could free some FPGA resources.
Any help as to how I can proceed with this i.e. reducing receiver
functionality and freeing up FPGA resources? Also if I should try
implementing some easy additonal functionalities in the FPGA,(so as to
not damage the USRP board) then which one should I go ahead with?
Are there any C++ blocks that I can try implementing in VHDL/Verilog code
in FPGA and improve performance?
I would be grateful if some of you could help me / point in the right
directions with the above questions.
Thanking you,
S Mande.
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Kutta Consulting, Inc.
www.kuttaconsulting.com
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