[Discuss-gnuradio] VHDL / Verilog Combination.

[S Mande]

Hi,


I scanned the Mailing List Archive and figured out that the code that goes inside USRP FPGA is Verilog code.

I personally know VHDL and was looking to make some changes to the FPGA code.

I was wondering if it is possible for the existing (USRP's) Verilog and my VHDL code to co-exist ? If yes, than do I need to make some special changes to the existing USRP Verilog code for both to coexist?

Or would it be advisable to code my new module in Verilog only?

Please excuse me if this sounds like a beginner questions.

Thanks.

S. Mande.