Re: [Discuss-gnuradio] atsc_cpll finally works

[Charles Swiger]

On Tue, 2008-05-20 at 21:55 -0400, Brian Padalino wrote:
> On Tue, May 20, 2008 at 9:38 PM, Charles Swiger <address@hidden> wrote:
> > The issue turned out to be jiggering the numbers that say "I strongly
> > suggest that you not mess with these..."   * by .707 for the bit timing
> > loop worked  ;)
> >

> Sorry, Chuck.  I am still not sure I understand the whole deal.  I am
> not even sure how a PLL is being used since it's all AM and there's no
> real phase information being transmitted - is there?
> 
> I was starting to read this:
> 
>     http://www.broadcast.net/~sbe1/8vsb/8vsb.htm
> 

Hi Brian - you are correct about 8vsb modulation - the document states:

"In 8-VSB, the digital information is transmitted exclusively in the
amplitude of the RF envelope and not in the phase. This is unlike other
digital modulation formats, such as QAM, where each point in the signal
constellation is a certain vector combination of carrier amplitude and
phase."


The part I'm wrestling with is the purely rf front end before we even
begin the 8vsb processing, specifically:


"The first "helper" signal is the ATSC pilot. Just before modulation, a
small DC shift is applied to the 8-VSB baseband signal (which was
previously centered about zero volts with no DC component). This causes
a small residual carrier to appear at the zero frequency point of the
resulting modulated spectrum. This is the ATSC pilot. This gives the RF
PLL circuits in the 8-VSB receiver something to lock onto that is
independent of the data being transmitted. "


We get a complex datastream from the usrp with signals from -3.2 to
+3.2Mhz (6.4Mhz wide, easy /10 decimation - Eric wants 8Mhz ;).
Previously we had to upconvert the spectrum to 5.75Mhz so that it's all
positive frequencies, then we take just the real part
(gr.complex_to_float) and then let the atsc_fpll lock onto the carrier
and shift it down to 0Hz and then the 8vsb demodulation magic starts
like you expected.     But why upconvert, then down-mix again? Why not
just make a pll that would lock onto the carrier when it's somewhere
around -3 + .31 Mhz and elimate one whole mixer?  That's what atsc_cpll
(complex in, real out) is for.

Now my question: Is it possible to tune the usrp so the carrier is at
+.31 Mhz ? (band center at 3, from -.2 to 6.2Mhz?)  Then we could run
the cpll at 6.4 or 8Msps and get another big performance boost, maybe.
Right now the pll at 19.2 Mhz (6.4 * 3) is an expensive part. Eric, I
guess the bit timing loop would work at 24Mhz (8 * 3).

--Chuck