Hi,
I've been trying to get two USRP2's with their clocks both synced to a
10MHz reference (for now the same reference from the back of some test
equipment) - to do this I'm using the following code:
in_pipe1=usrp2.source_32fc('eth0')
in_pipe2=usrp2.source_32fc('eth2')
in_pipe1.config_mimo(usrp2.MC_WE_LOCK_TO_SMA)
in_pipe2.config_mimo(usrp2.MC_WE_LOCK_TO_SMA)
As a quick test I then connected each usrp2 to a complex oscilloscope
(i.e scopesink2.scope_sink_c)
This sort of works -- checking on the test clock pins on each USRP2 the
100MHz clocks are locked.
Unfortunately putting in a sine wave from a lab sig gen garbage is seen
-- a constant DC signal on the BasicRX and what looks like modulated
noise on the DBSRX (testing at different frequencies on both boards) --
the signal looks as expected if the config_mimo line is commented (and
the usrp2's restarted).
Am I missing something obvious?