It is my understanding that the current FPGA image used for OpenBTS
will fail on the transmit side if the FPGA clock is slower than the
USB clock. The USB clock is 48 MHz.
If you (or anyone else involved) can provide the details of what the
issue is here, I may have some time to dive in and potentially come up
with a fix. Let me know if interested.
Also, the GSM symbol clock is derived from 13 MHz, so if you use a
multiple-of-13 clock, you can simplify a lot of the decimation.
These two facts together led us to choose 52 MHz for the current
OpenBTS USRP clock.
Gotcha. Thanks for the quick response David.
Anyone else know of any other issues that would prevent the FPGA from
being clocked at lower speeds?