[Discuss-gnuradio] Minimum external clock for FPGA?
From:
John Orlando
Subject:
[Discuss-gnuradio] Minimum external clock for FPGA?
Date:
Sat, 16 Jan 2010 17:33:07 -0600
Hi all, I've seen posts about folks providing an external clock of 44 MHz to the USRP, and with a few software tweaks, getting it to work. I'm wondering if there is a floor as to how low this clock be reduced without causing problems. I know some A/D converters have minimum sample rates, but the AD9862 datasheet doesn't seem to indicate that it does. Is there any reason I couldn't run my USRP with an external reference at 26 MHz? How 'bout 10 MHz?
The only datapoint I could find was a reference to the fact that the current openBTS FPGA image doesn't run (?) at 26 MHz due to a "firmware fix" that is needed, though I'm guessing that is referencing the FPGA code:
I'll probably make the USRP hardware modification on Monday to try these out with an external sig gen, but I figured I'd throw the question to the list prior to that to see if I could get a definitive answer.