I am trying to syncronise data acquisition for 3 USRP2 boxes at 2.4GHz to
aquire say 1M samples from each board and write to a text file. So far I
have managed to modify the firmware to output the USRP2 clock to the debug
pins and to call config_mimo(WE_LOCK_TO_SMA) and sync_to_pps(). When I
connect a 10MHz 2v Pk-Pk sine wave to each board (No PPS signal) and look at
the clock output pin for each there is no drift in waveforms with respect to
one another and the external clock reference. However, there is a phase
offset between the clock edges on each board which changes every time they
are reset (sometimes of half a clock period).
Please see the example which includes the external clock reference and 3
clock outputs.
Wont this mean that I have unsyncronised sampling since the ADC is
controlled by the position of the clock edge?
Is there a way to overcome this problem?
My current python script to read in parallel is derived from the example
/gr-utils/src/python/usrp2_rx_cfile.py using gr.hier_block2 to create
multiple flow graphs (usrp2 -> text file replicated four times). Do I need
any special syncronisation functions in here or should the problem be fully
handled on the firmware/FPGA?
Best regards,
Marc.
http://old.nabble.com/file/p27642862/scope_plot.jpg