Ettus Research is very excited to announce the release of RFNoC!
Modern FPGAs, like the Xilinx Kintex-7 and ZYNQ used in third generation USRPs have incredible computational capability, but taking advantage of that capability is difficult at best when using traditional FPGA design flows.
RFNoC (which stands for RF Network on Chip) provides the capability to create FPGA applications as easily as you create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data to & from an FPGA in your application, dramatically improving the ease of FPGA off-loading.
Here is an example of an RFNoC flowgraph built using the GNU Radio Companion. With four blocks, data is being generated on the host, off-loaded to the FPGA for filtering, and then brought back to the host for plotting:
Signal processing algorithms are encapsulated in easy-to-use wrappers which allow them to be dynamically connected and used as needed. Fixed routing is eliminated. Mixing and matching host-based and FPGA-based processing is transparent to the user, and that processing can scale across multiple FPGAs and devices across a network. You can now make custom FPGA designs without ever needing to write Verilog or VHDL!
RFNoC has been integrated into UHD for our third generation USRPs (X300-series, E300-series, and future devices), enabling you to share FPGA designs across devices easily. Additionally, we have integrated support for RFNoC into GNU Radio and GRC, so you can now graphically design mixed host- and FPGA-based flowgraphs.
Watch an RFNoC presentation and demo from GRCon14: (long, but HIGHLY recommended as an intro)
All documentation and links to the source code can be found here:
A paper from ACM SIGCOMM with more background:
If you have any questions, please don't hesitate to ask. We plan to hold most of the RFNoC-related discussion on the usrp-users mailing list.
Matt Ettus
President, Ettus Research