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From: | Yeo Jin Kuang Alvin (IA) |
Subject: | Re: [Discuss-gnuradio] Ettus E310 sample rate |
Date: | Tue, 15 May 2018 00:51:32 +0000 |
Hi all, Does this apply to the B210 too? That is correct, handling data at a rate much higher than 8 MS/s will require moving DSP into the FPGA. UHD comes with a variety of example RFNoC blocks. The fosphor block for instance produces a real time spectrum
analyzer plot of the full 61.44 MS/s of the E310. Thanks in advanced! From: Discuss-gnuradio [mailto:discuss-gnuradio-bounces+address@hidden
On Behalf Of Derek Kozel Hello Laura, That is correct, handling data at a rate much higher than 8 MS/s will require moving DSP into the FPGA. UHD comes with a variety of example RFNoC blocks. The fosphor block for instance produces a real time spectrum
analyzer plot of the full 61.44 MS/s of the E310. Regards, Derek On Mon, May 14, 2018 at 3:57 PM, Laura Huddleston <address@hidden> wrote: So just to clarify, I would need to program the FPGA explicitly if I want to achieve
a sample rate of higher than 8MS/s? ~~~~~~~~~~~~~~~~~~~~~ Laura Huddleston From:
Derek Kozel <address@hidden>
Hello Laura, The ADCs and DACs do support running at 61.44 MS/s. However the ARM processor is not able to handle data traffic at that rate so some of the processing must be done
in the FPGA. Depending on the application about 10 MS/s is an achievable rate. Both 12 MS/s and 8 MS/s are not integer divisors of 61.44 MHz so the ADC rate is being changed behind the scenes to support those rates, probably to 16 or 32 MHz. You
can explicitly set that by adding an argument to the benchmark_rate or similar utility. Regards, Derek On Fri, May 11, 2018 at 7:37 PM, Laura Huddleston <address@hidden> wrote:
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