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Re: Some introductory docs about C level threading

From: Ken Raeburn
Subject: Re: Some introductory docs about C level threading
Date: Tue, 1 Feb 2005 19:38:03 -0500

On Feb 1, 2005, at 18:40, Kevin Ryde wrote:
Ken Raeburn <address@hidden> writes:
 -> (....x)[0] = ((... i >> 2) << 2 + scm_tc2_int)
-> copy i, masking off bottom two bits, into target location; then add
in scm_tc2_int

Any sensible compiler should do the one store that's given, and the

Not if you have an architecture where memory-to-memory arithmetic operations are cheap and registers are few. By "copy i, masking" I didn't mean "copy to register, do the mask, then store", I meant something like "andl (r0),i,-4; addl (r0),2".

In fact, for one architecture I've got in mind, another two-instruction sequence, a simple memory-to-memory copy followed by overwriting just the low two bits, would also do the trick. As it happens, that architecture isn't especially register-starved, but one could probably construct a function using a lot of temporaries and increase pressure on the register allocator such that it might still be worth avoiding the register temporary. (Sorry, I've done a little compiler hacking in my time...)

SCM type will mean it's atomic.

If use of the SCM type is assumed to be atomic in terms of CPU memory access and inter-CPU memory consistency, that's fine, but it should be documented as such -- and we should acknowledge that ports to architectures where that assumption does not hold may not be possible.

You can force load/stores to be exactly as given using `volatile', but
as far as I can tell this particular example shouldn't need that.

The problem is, if there are any case where it would be needed, then we need to use it everywhere there could be a potential problem. Depending on just how it works out, that could mean essentially declaring some of the scheme object types (like cons cells) as volatile, which would be poor for performance.

And volatile declarations may fix the possibility of storing incomplete values, but I don't think it would deal with the cross-thread memory access ordering issue.


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