Append dependencies through variables

[Riccardo Manfrin]

Hi list,
I have the following main makefile:

#Makefile

include Makefile1

all: $(MAKE_DEPS_ALL)
    @echo $(MAKE_DEPS_ALL)

#End of Makefile



and Makefile1 file

#Makefile1

MAKE_DEPS_ALL+=mydep

mydep:
    $(MAKE) -C /my/path

#End of Makefile1



Unfortunately, mydep dependency is not resolved. I see "mydep" when I 
print MAKE_DEPS_ALL, but the depencency is not looked up.
If, instead, I try to hardcode the depencency straight (like this: "all: 
mydep"), everything works. Why isn't make resolving the depencency?
What I'd like is for included Makefiles to have a way to append their 
own dependencies without touching the main Makefile.

Thanks in advance.
R