Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[goldsimon]

Jan Menzel wrote:
>For TX there is nothing really needed on the LWIP side. Draining the
>d-cache is always possible without side effects. Its just a question of
>efficiently if a packet content does not start at a cache line.

Unless that buffer would be in the same cache line as an rx buffer, yes.

>       For RX the Ethernet data part has to be aligned to cache line to void
>issues due to cache invalidation.
>       In my implementations I use pooled memory. From the lwip code I can
>see, that LWIP_MEM_ALIGN_SIZE() is used to add padding between
>management data and actual free space. If this Macro is used to force
>cache-line alignment, it would be already possible to use zero-copy RX
>with cache.

Since the same alignment is used everywhere, you would introduce much useless 
padding all over the place and use much not memory than necessary.

What we really need is a dedicated, different alignment here.

Simon