Re: [lwip-users] Problem running lwip on cortex M7 with D cache enabled

[Jan Menzel]

On 01.12.2017 17:26, goldsimon wrote:
>>      For RX the Ethernet data part has to be aligned to cache line to void
>> issues due to cache invalidation.
>>      In my implementations I use pooled memory. From the lwip code I can
>> see, that LWIP_MEM_ALIGN_SIZE() is used to add padding between
>> management data and actual free space. If this Macro is used to force
>> cache-line alignment, it would be already possible to use zero-copy RX
>> with cache.
> 
> Since the same alignment is used everywhere, you would introduce much useless 
> padding all over the place and use much not memory than necessary.
> 
> What we really need is a dedicated, different alignment here.
> 
Two options without modifications to LWIP (even though it could make
thinks easier)
1) align buffers with d-cache line size and flush struct
memp_malloc_helper before actual rx. (makes the assumption that struct
memp_malloc_helper does not change while rx)
2) align buffers to -sizeof(struct memp_malloc_helper) and pad size
such, that the used part is aligned and struct memp_malloc_helper is in
its own cache line. This way RX goes into its own unshared d-cache lines
with can be safely invalidated.

Jan